Due to the mix of Processing Subsystem (PS “MIO”) and Programmable Logic (PL “EMIO”) I/O—in addition to the reconfigurability of the FPGA pins—there is no straightforward answer to this question.
However, there are some high-level numbers provided in the Zynq product specification documentation that can be used as a baseline.
The MIO (PS), which are 1.8V on snickerdoodle, have a max current rating of 8mA.
The EMIO (PL) can be driven at 4, 8, or 12mA for LVCMOS12; 4, 8, 12, or 16mA for LVCMOS15, LVCMOS25, or LVCMOS33; and 4, 8, 12, 16, or 24mA for LVCMOS18 or LVTTL.
Differential standards (e.g. LVDS_25) aren’t defined in terms of output current, but rather in terms of developing a certain differential voltage across the reference 100-ohm load.
For more information, we encourage you to explore DS187 from Xilinx (specifically pages 10–12).