snickerdoodle has 16 differential ADC pairs spread across two FPGA I/O connectors: JA1 and JA2. These 16 channels are multiplexed into 2x 1MSPS 12-bit ADCs.
Reference the snickerdoodle pinout tables on our documentation page for a list of the exact pins/pairs (look for pins with “AD” in the FPGA Signal name—e.g. AD1P/AD1N).
The Zynq-7000 User Guide UG480 provides more helpful information on the ADC and DAC specifications.
The DAC comes from the STM32 platform controller (U11) via J2.3 and J2.4. The multiplexed ADC input also goes to this connector (J2.1 and J2.2/VP_0 and VN_0).